BUS AND MEMORY TRANSFERS
BUS AND MEMORY TRANSFERS
A typical digital computer has many registers, and paths
must be provided to transfer in formation form one register to another. The
number of wires will be excessive if separate lines are used between each
register and all other registers in the system. A more efficient scheme for
transferring information between registers in a multiple-register configuration
is a common bus system. A bus structure consists of a set of common lines, one
for each bit of a register, through which binary information is transferred one
at a time. Control signals determine which register is selected by the onus
during each particular register transfer.
One way of constructing a common bus system is with
multiplexers. The multiplexers select the source register whose binary
information is then placed on the bus. The construction of a bus system for four
registers is shown is Fig . Each register has four bits, numbered 0 through 3.
The bus consists of four 4 × 1 multiplexers each having four data inputs, 0
through 3, and two selection inputs, S1 and S0. In order not to complicate the
diagram with 16 lines crossing each other, we use labels to show the
connections from the outputs of the registers to the inputs of the
multiplexers. For example, output 1 of register A is connected to input 0 of
MUX 1 because this input is labeled A1. The diagram shows that the bits in the
same significant position in each register are connected to the data inputs of
one multiplexer to form one line of the bus. Thus MUX 0 multiplexes the four 0
bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and
similarly for the other two bits.
The two selection lines S1 and S0 are connected to the
selection inputs of all four multiplexers. The selection lines choose the four
bits of one register and transfer them into the four line common bus. When S1
S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to
the outputs that form the bus. This causes the bus lines to receive the content
of register A since the outputs of this register are connected to the 0 data
inputs of the multiplexers. Similarly, register B is selected if S1S0 = 01, and
so on. Table shows the register that is selected by the bus for each of the
four possible binary value of the selection lines.
In general, a bus system will multiples k registers of n
bits each to produce an n-line common bus. The number of multiplexers needed to
construct the bus is equal to n, the number of bits in each register. The size
of each multiplexer must be k ×1 since it multiplexes k data lines. For
example, a common bus for eight registers of 16 bits each requires 16
multiplexers, one for each line in the bus. Each multiplexer must have eight
data input lines and three selection lines to multiplex one significant bit in
the eight registers.
Figure: Bus system for four registers:
Table
Function Table for Bus of Fig:
The transfer of information from a bus into one of many
destination registers can be accomplished by connecting the bus lines to the
inputs of all destination registers and activating the load control of the
particular destination register selected. The symbolic statement for a bus
transfer may mention the bus or its presence may be implied in the statement.
When the bus is includes in the statement, the register transfer is symbolized
as follows:
BUS ← C, R1 ← BUS
The content of register C is placed on the bus, and the
content of the bus is loaded into register R1 by activating its load control
input. If the bus is known to exist in the system, it may be convenient just to
show the direct transfer.
R1 ← C
From this statement the designer knows which control signals
must be activated to produce the transfer through the bus.
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